Control behaviour of the input/output shift registers for state machine 0
| IN_COUNT | Set the number of pins which are not masked to 0 when read by an IN PINS, WAIT PIN or MOV x, PINS instruction. For example, an IN_COUNT of 5 means that the 5 LSBs of the IN pin group are visible (bits 4:0), but the remaining 27 MSBs are masked to 0. A count of 32 is encoded with a field value of 0, so the default behaviour is to not perform any masking. Note this masking is applied in addition to the masking usually performed by the IN instruction. This is mainly useful for the MOV x, PINS instruction, which otherwise has no way of masking pins. |
| FJOIN_RX_GET | If 1, disable this state machine’s RX FIFO, make its storage available for random read access by the state machine (using the If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO’s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. |
| FJOIN_RX_PUT | If 1, disable this state machine’s RX FIFO, make its storage available for random write access by the state machine (using the If FJOIN_RX_PUT and FJOIN_RX_GET are both set, then the RX FIFO’s registers can be randomly read/written by the state machine, but are completely inaccessible to the processor. Setting this bit will clear the FJOIN_TX and FJOIN_RX bits. |
| AUTOPUSH | Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH. |
| AUTOPULL | Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH. |
| IN_SHIFTDIR | 1 = shift input shift register to right (data enters from left). 0 = to left. |
| OUT_SHIFTDIR | 1 = shift out of output shift register to right. 0 = to left. |
| PUSH_THRESH | Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place. Write 0 for value of 32. |
| PULL_THRESH | Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place. Write 0 for value of 32. |
| FJOIN_TX | When 1, TX FIFO steals the RX FIFO’s storage, and becomes twice as deep. RX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. |
| FJOIN_RX | When 1, RX FIFO steals the TX FIFO’s storage, and becomes twice as deep. TX FIFO is disabled as a result (always reads as both full and empty). FIFOs are flushed when this bit is changed. |